`timescale 1ns / 1ps

module sim_138;

	// Inputs
	reg A;
	reg B;
	reg C;
	reg G1;
	reg G2A_L;
	reg G2B_L;

	// Outputs
	wire Y0_L;
	wire Y1_L;
	wire Y2_L;
	wire Y3_L;
	wire Y4_L;
	wire Y5_L;
	wire Y6_L;
	wire Y7_L;

	// Instantiate the Unit Under Test (UUT)
	xmj74x138 uut (
		.A(A), 
		.B(B), 
		.C(C), 
		.G1(G1), 
		.G2A_L(G2A_L), 
		.G2B_L(G2B_L), 
		.Y0_L(Y0_L), 
		.Y1_L(Y1_L), 
		.Y2_L(Y2_L), 
		.Y3_L(Y3_L), 
		.Y4_L(Y4_L), 
		.Y5_L(Y5_L), 
		.Y6_L(Y6_L), 
		.Y7_L(Y7_L)
	);

	initial begin
		G1=0;
		G2A_L=0;
		G2B_L=0;
		{C,B,A}=3'b000;

		#100;
		{C,B,A}=3'b111;

		#100;
		G1=1;
		{C,B,A}=3'b000;

		#100;
		{C,B,A}=3'b001;

		#100;
		{C,B,A}=3'b010;

		#100;
		{C,B,A}=3'b011;

		#100;
		{C,B,A}=3'b100;

		#100;
		{C,B,A}=3'b101;

		#100;
		{C,B,A}=3'b110;

		#100;
		{C,B,A}=3'b111;

	end
      
endmodule

